Conventional Metal Oxide Semiconductor (MOS) transistors for use in semiconductor devices are typically constructed with the gate being formed on a top surface of the semiconductor substrate. FIG. 1 is a cross-sectional view of a cell structure of a conventional MOS transistor 100 including a substrate 102 of a semiconductor crystal such as silicon. The transistor 100 also includes a channel region 104, a source region 106, a drain region 108, a gate dielectric layer 110, and a gate electrode 112. As shown in FIG. 1, the gate dielectric layer 110 and the gate electrode layer 112 are disposed on a top surface of the substrate 102.
As semiconductor devices and integrated circuits are scaled down in size, demands for the efficient use of space have increased. Heretofore, conventional MOS circuits have utilized a device structure in which the transistor gate is formed on a top surface of the silicon substrate as shown in FIG. 1. However, this type of device structure is limited in the degree to which active devices can be made smaller in order to improve packing density and performance.